DDR SDRAM for stable read operation

摘要

A global input/output precharge apparatus includes a latch for cross-coupling and latching a global input/output line and a complementary global input/output line; a global input/output line delay for delaying the global input/output line and the complementary global input/output line by a predetermined time delay; a global input/output line precharge logic for pre-charging the global input/output line feed-backed from the global input/output line delay; a first precharge logic for applying a power voltage to the global input/output line when a first logic state is feed-backed on the output of the global input/output line precharge logic and applying a ground voltage to the global input/output line when a second logic state is feed-backed on the output of the global input/output line precharge logic; and a second precharge logic for applying the power voltage to the complementary global input/output line when the first logic state is feed-backed on the output of the global input/output line precharge logic and applying the ground voltage to the complementary global input/output line when the second logic state is feed-backed on the output of the global input/output line precharge logic.