发明名称 DYNAMIC PHASE LOGIC GATE
摘要 A logic device for use with data signals having a continuously or semi-continuously varying waveform of substantially fixed frequency. The device provides a logical output from at least one of the data inputs and comprising a first pair of inputs each to receive a data signal having one of a predetermined set of values representing analog, discrete, or digital states. A combiner stage is used to combine the inputs and produce a signal therefrom. A filter stage is utilized to receive the signal and produce a conditioned signal representative of one of a pair of binary states. The conditioned signal is combined with a second control input. The resultant signal is passed to an output.
申请公布号 WO0167607(A2) 申请公布日期 2001.09.13
申请号 WO2001CA00293 申请日期 2001.03.07
申请人 ROMANIUK, CHARLES, C. 发明人 ROMANIUK, CHARLES, C.
分类号 G02F3/00;H03K19/02;(IPC1-7):H03K19/00 主分类号 G02F3/00
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