发明名称 Semiconductor device using external power voltage for timing sensitive signals
摘要 A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.
申请公布号 US6288585(B1) 申请公布日期 2001.09.11
申请号 US20000535745 申请日期 2000.03.27
申请人 FUJITSU LIMITED 发明人 BANDO YOSHIHIDE;TANIGUCHI NOBUTAKA;TOMITA HIROYOSHI;HARA KOTA;SHINOZAKI NAOHARU
分类号 G11C11/413;G11C7/10;G11C7/22;H03L7/081;(IPC1-7):H03L7/06 主分类号 G11C11/413
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