Layout synopsizing process for efficient layout parasitic extraction and circuit simulation in post-layout verification

摘要

A process is provided for generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for a system having a plurality of repetitive subcircuits. The process includes the steps of: receiving an input layout database including a plurality of geometric objects including cells representing the IC design, each of the cells including a plurality of polygons; identifying a plurality of repetitive cells of the input layout database, the repetitive cells being associated with the repetitive sub-circuits; recognizing at least one pattern of the repetitive cells; defining at least one cut region of the input layout database, the cut region being defined by physical layout coordinates, the cut region intersecting a corresponding pattern of the repetitive cells; and generating a synoptic layout database.