发明名称 |
Bias circuit for read amplifier circuits for memories |
摘要 |
A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.
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申请公布号 |
US6288960(B1) |
申请公布日期 |
2001.09.11 |
申请号 |
US20000686326 |
申请日期 |
2000.10.11 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
CONTE ANTONINO;GAIBOTTI MAURIZIO;ZERILLI TOMMASO |
分类号 |
G11C7/06;G11C7/14;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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