Technique for controlling system bus timing with on-chip programmable delay lines

摘要

An on-chip programmable delay line is provided for controlling timing of an embedded system. A delay register is coupled to a processor. The delay register stores a delay or control value responsive to the processor. The on-chip programmable delay line is coupled to the delay register and delays a signal responsive to the delay value. The relationship between dynamic random access memory (DRAM) signals, such as row address strobe (RAS) and column address strobe (CAS), can thus be adjusted. In addition, the on-chip programmable delay line can be utilized with a device that includes an input that is not synchronous to a system clock.