| 摘要 |
PURPOSE: To accelerate the speed of a D-FF circuit to operate on the basis of clock signal generated in a clock generating circuit. CONSTITUTION: A clock generator circuit 2 is composed of two inverters and a buffer and generates plural clock signals (CLK, /CLK1,/CLK2, CLK2) having different generation timing. A slave flip-flop starts operating on the basis of the clock signals (CLK and /CLK1) of early generation timing among the clock signals generated in the clock generating circuit and a master flip-flop stops operating on the basis of the clock signals (/CLK2 and CLK2) of late generation timing among the clock signals generated in the clock generator circuit.
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