发明名称 SERIAL RECEIVER
摘要 PROBLEM TO BE SOLVED: To secure processing time except for serial receiving during serial receiving of a CPU and to separate processing with error detection in the interruption program of the CPU after serial receiving. SOLUTION: While serially receiving plural bytes, received data are stored in a FIFO 107 and after the receiving end interruption of plural bytes occurs and a receiving error decision inside the FIFO 107 is performed, the received data are read out. By deciding the values of a framing error flag 104 and a parity error flag 105 which are not cleared until reading-out after setting, the presence/absence of a receiving error in the data stored in the FIFO is investigated. Thus, processing with the error detection in the interruption program can be separated and the processing time except for serial receiving of the CPU can be secured during serial receiving.
申请公布号 JP2001244915(A) 申请公布日期 2001.09.07
申请号 JP20000053047 申请日期 2000.02.29
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 UMEI TOSHITOMO;MORIKAWA TORU
分类号 G06F13/00;G06F9/46;G06F9/48;G06F11/00;H04L1/00;H04L13/08;H04L29/02 主分类号 G06F13/00
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