| 摘要 |
The integrated circuit has a clock input for an external clock signal and an output unit controlled by an internal clock signal in a normal mode of operation to output data to a data output. In addition, the integrated circuit has a control unit generating the internal clock signal from the external clock signal. The control unit has a phase shift unit that, in the normal mode of operation, effects a phase shift of the internal clock signal generated by the control unit with respect to the external clock signal. In addition, the integrated circuit has a detector unit determining the capacitive load on the data output. The detector unit supplying the phase shift unit with a corresponding detector signal on the basis of which the phase shift is set. |
