| 摘要 |
Disclosed is a semiconductor memory device comprising: a memory cell array formed of cell blocks arranged in matrix of row and column; sub wordline drivers, interposed between the cell blocks arranged along column direction, each for driving a row of the cell blocks in response to a wordline drive signal; and wordline drive signal generators, disposed between the sub wordline drivers arranged along row direction, each for providing the wordline drive signal to the corresponding sub wordline driver. The wordline drive signal generators have different drive capabilities depending upon the number of wordline drivers to be driven by the generators.
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