发明名称 Stacked semiconductor integrated circuit device and manufacturing method thereof
摘要 The present invention provides a semiconductor integrated circuit having excellent junction characteristics when applying the silicide technology to an extremely narrowed diffusion layer between adjacent gate electrodes as well as a method for manufacturing the same. To attain this object, a configuration of the invention has electrode layers formed on a semiconductor substrate, sidewall layers formed on the side walls of electrode layers, and high-melting point metal silicide layers formed on the electrode layers, wherein the sidewall layers are connected together. This makes it possible to eliminate abnormal growth during silicide formation because of the fact that the region defined between the electrode layers on the substrate is covered by the sidewall layers.
申请公布号 US2001019162(A1) 申请公布日期 2001.09.06
申请号 US20010813807 申请日期 2001.03.22
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 ASAMURA TAKESHI
分类号 H01L21/28;H01L21/3205;H01L21/336;H01L21/768;H01L21/8238;H01L23/522;H01L29/78;(IPC1-7):H01L29/76 主分类号 H01L21/28
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