发明名称 |
Clock regeneration circuit and optical signal receiver using the same |
摘要 |
Disclosed is a clock regeneration circuit comprising a PLL circuit which includes a voltage control oscillator, for synchronizing an oscillation frequency signal of the voltage control oscillator with a phase of a reception signal; a clock extraction circuit which includes a band passing filter having a passing band width which concurrently extracts a basic waves component of the oscillation frequency signal of the voltage control oscillator and a harmonic component of a dividing signal of the oscillation frequency signal, for extracting a clock component of the reception signal; a frequency detector for detecting a different in frequencies between an output of the clock extraction circuit and an oscillation frequency of the voltage control oscillator; a filter for controlling the oscillation frequency of the voltage control oscillator of the PLL circuit at a detection output of the frequency detector; a bit rate detection circuit for detecting a bit rate of the reception signal; and a frequency selection circuit for outputting an oscillation frequency of the voltage control oscillator of the PLL circuit or a frequency signal obtained by dividing the oscillation frequency in response to the bit rate detected by the bit rate detection circuit, as a regeneration clock signal.
|
申请公布号 |
US2001019441(A1) |
申请公布日期 |
2001.09.06 |
申请号 |
US20000729949 |
申请日期 |
2000.12.06 |
申请人 |
KOGURE KAZUHISA;YAMADA HIROSHI;SUDA ATSUSHI |
发明人 |
KOGURE KAZUHISA;YAMADA HIROSHI;SUDA ATSUSHI |
分类号 |
H03L7/113;H03L7/087;H04B10/00;H04B10/04;H04B10/06;H04B10/14;H04B10/158;H04B10/26;H04B10/28;H04J14/00;H04J14/02;H04L7/027;H04L7/033;(IPC1-7):H04B10/00 |
主分类号 |
H03L7/113 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|