| 摘要 |
A ferroelectric memory has a memory cell array including at least three memory cells composed of a ferroelectric capacitor, and first and second transistors connected in parallel to one electrode of the ferroelectric capacitor, a first bit line to which the ferroelectric capacitors of the memory cells are connected in parallel via the first transistors, and a second bit line to which the ferroelectric capacitors of a plurality of memory cells are connected via the second transistors. The ferroelectric memory has a decision device for comparing a voltage of the first bit line and a voltage of the second bit line to each other to decide whether data is a logical "1" or a logical "0". Thus, deterioration of dummy cells which undergo larger numbers of reads than data cells is suppressed and, as a result, an intermediate voltage can correctly be generated.
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