发明名称 Power level calculation for AGC in a receiver circuit so as to avoid ADC saturation and correction via power calculation after filtering
摘要 <p>Power level calculating circuit 10 and 11 calculate power levels at the input and output terminals, respectively, of a channel filter 6, and an adder 13 computes the difference between the two calculated power levels. An adder 13 corrects (i.e., subtracts) the difference obtained in the adder 12 from an AGC control signal output of an integrating circuit 9, and reports the correction output as antenna terminal reception power level to a base-band circuit 7. The correction output of the adder 13 is obtained by taking the extent of attenuation outside a desired wave band in the channel filter 6, and thus corresponds to accurate antenna terminal reception power level.</p>
申请公布号 GB2359948(A) 申请公布日期 2001.09.05
申请号 GB20000030062 申请日期 2000.12.08
申请人 * NEC CORPORATION 发明人 KAZUHIRO * KURIHARA
分类号 H03G3/20;H03G3/30;H04B1/04;H04B1/16;H04B1/18;H04B7/005;H04B17/00;H04J13/00;H04L27/01;(IPC1-7):H03G3/20 主分类号 H03G3/20
代理机构 代理人
主权项
地址