发明名称 Method and device for limiting the substrate potential in junction isolated integrated circuits
摘要 This invention concerns integrated circuits with junction insulation, and in particular relates to a method and a device for attenuating parasitic effects in junction insulated integrated circuits. The device comprises at least one substrate contact connected to a reference potential, and at least one unidirectional element connected between the substrate contact and the reference potential. <IMAGE>
申请公布号 EP1130648(A1) 申请公布日期 2001.09.05
申请号 EP20000830155 申请日期 2000.02.29
申请人 STMICROELECTRONICS S.R.L. 发明人 ALAGI, FILIPPO
分类号 H01L27/02 主分类号 H01L27/02
代理机构 代理人
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