Semiconductor memory device with reduced current consumption in data hold mode

摘要

A power supply circuit (22c) generating a power supply voltage for refresh-related circuitry (14a) and a power supply circuit (22b) for column-related/peripheral control circuitry (14b) are controlled by a power supply control circuit (25) to be put in different power supply voltage supplying states in a self refresh mode. In the self refresh mode, only self refresh-related circuitry receives a power supply voltage to perform refresh operation. A reduced current consumption can be achieved in the self refresh mode while fast access operation is not deteriorated. <IMAGE>