A GATED STORE BUFFER FOR AN ADVANCED MICROPROCESSOR

摘要

A gated store buffer including circuitry for temporarily holding apart from other memory stores all memory stores sequentially generated during a translation interval by a host processor translating a sequence of target instructions into host instructions, circuitry for transferring memory store s sequentially generated during a translation interval to memory if the translation executes without generating an exception, circuitry for indicati ng which memory stores to identical memory addresses are most recent in respons e to a memory access at the memory address, and circuitry for eliminating memo ry stores sequentially generated during a translation interval if the translati on executes without generating an exception.