Hidden refresh pseudo SRAM and hidden refresh method

摘要

A hidden refresh 2P2N pseudo SRAM having an array of memory cells. Each of the memory cells includes a cross-couple latch and two PMOS access transistors. The cross-couple latch are structured with two NMOS transistors which are cross coupled to each other and provided to store a pair of signals. The two NMOS transistors have their sources connected to a negative source voltage, and their drains and gates cross coupled to each other. The two PMOS transistors are controlled by a word line and provided to respectively access the two NMOS transistors of the cross-couple latch and a pair of bit lines. The two PMOS transistors have their sources connected to the pair of bit lines and drains connected to the drains of the two NMOS transistors, respectively.