发明名称 |
Memory architecture for automatic test equipment using vector module table |
摘要 |
A tester having a fast but flexible pattern generator which is implemented using readily available memories. The tester includes a pattern memory which holds test vectors. The vectors are organized into modules. The order of execution of the modules is selected from a list stored in memory. In the preferred embodiment, memories which operate in burst mode are used to implement the pattern memory. To compensate for the decrease in data rate which occurs when execution switches between modules in the middle of a burst, the memory refresh rate is dynamically altered upon switching between modules. |
申请公布号 |
US6286120(B1) |
申请公布日期 |
2001.09.04 |
申请号 |
US19940299753 |
申请日期 |
1994.09.01 |
申请人 |
TERADYNE, INC. |
发明人 |
REICHERT PETER A.;BROWN BENJAMIN J. |
分类号 |
G01R31/319;G11C29/36;(IPC1-7):G06F11/00 |
主分类号 |
G01R31/319 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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