| 摘要 |
A compact sub cooling method and apparatus arranged for simultaneously sub cooling both a processor and it companion voltage regulator for enhanced performance. A preferred embodiment of the invention provides for advantageous arrangement of the voltage regulator and memory proximate to the processor for high speed operation. In a preferred embodiment, a circuit board arrangement includes a processor requiring at least one bias voltage, and further includes a companion voltage regulator for providing the bias voltage. The voltage regulator is arranged sufficiently proximate to the processor, so as to limit inductance of electrical coupling therebetween. In a preferred embodiment, a piggy-back design is utilized, wherein the voltage regulator is stacked on top of the processor. Furthermore, a sub cooling module is utilized to simultaneously sub cool both the processor and the voltage regulator below ambient temperature, thereby potentially enhancing the performance of both components. In a preferred embodiment, an evaporator module is sandwiched between the voltage regulator and processor, and the evaporator module interoperates with a compressor and condenser to accomplish sub cooling of the voltage regulator and processor components.
|
