发明名称 |
Signal processor delta-sigma modulator stage |
摘要 |
A 1-bit nth order Delta Sigma Modulator where n is at least one comprises a linear signal processing section (50) which processes the 1-bit signal and produces a p bit output, a filter (52) which filters the p bit signal, an adder (53) a quantizer Q coupled to the output of the adder (53) to quantize a p bit signal to a 1-bit output signal, and a noise shaping section 51 which feeds the 1-bit output signal back to the adder 53.
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申请公布号 |
US6286020(B1) |
申请公布日期 |
2001.09.04 |
申请号 |
US19970979761 |
申请日期 |
1997.11.26 |
申请人 |
SONY CORPORATION;SONY UNITED KINGDOM LIMITED |
发明人 |
EASTTY PETER CHARLES;SLEIGHT CHRISTOPHER;THORPE PETER DAMIEN;ANGUS JAMES ANDREW SCOTT |
分类号 |
H03M7/32;(IPC1-7):G06F17/10 |
主分类号 |
H03M7/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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