发明名称 Digital clock recovery loop
摘要 A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method including using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal; extracting a clock from an input digital signal; and performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.
申请公布号 US6285261(B1) 申请公布日期 2001.09.04
申请号 US20000610177 申请日期 2000.07.05
申请人 MICRON TECHNOLOGY, INC. 发明人 PAX GEORGE E.;O'TOOLE JAMES E.;GRIFFIN DAN M.
分类号 H03L7/089;H03L7/113;H04B1/707;H04L7/033;(IPC1-7):H03L1/00 主分类号 H03L7/089
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