| 摘要 |
A burn-in test circuit for semiconductor memory device consisting of a memory cell array having a plurality of memory cells and a row decoder for outputting a word line drive signal so as to drive word lines of the memory cell array, includes a reference voltage generating unit for generating a reference voltage/a voltage sensing unit for sensing a power supply voltage level; a self-refresh timer for outputting a clock signal; a burn-in control unit for outputting a burn-in enable signal according to the output signal from the voltage sensing unit and the output signal from the self-refresh timer; an auto-refresh address counter for generating an internal address signal according to the burn-in enable signal of the burn-in control unit and the auto-refresh command; and a multiplexer for multiplexing the external address signal and the internal address signal under the control of the auto-refresh command and the burn-in control signal. In the semiconductor memory device using the burn-in test circuit of the present invention, the word lines are driven by controlling the level of the external power supply voltage VCC, rather than performing a burn-in testing according to an externally generated command, so that burn-in testing can be performed at the wafer and the package level at a low expense with high efficiency.
|
