Verification method by means of comparing internal state traces

摘要

A chip verification method by comparing internal state traces of chips having various functions, which is capable of reducing the overall chip designing and verifying time and attaining a more exact verification. The chip verification method in a chip design stage includes a first step of executing an application program for each of a target system having a target chip and a system having a function verification chip model of a design stage, using a virtual system modeled by a hardware description language; a second step of storing an internal state of the target chip on a command-by-command basis during execution of the application program and generating a trace file; a third step of comparing the internal state of the target chip stored at the trace file and an internal state of the function verification chip model on a command-by-command basis; and a fourth step of continuing execution of the program if the respective internal states are the same from the above comparison result, and if different, outputting the internal state and ending execution.