| 摘要 |
A dummy memory cells for high-accuracy self-timing circuit in dual-port SRAM is disclosed herein. The dummy memory cells mentioned above include a plurality of word lines, two pairs of bit lines, two pairs of load circuits and an array of dummy memory cells. The plurality of word lines is utilized to receive an access signal, the two pairs of load circuit are connected to the two pairs of bit lines respectively for applying to a voltage source. The array of dummy memory cells includes a first group of dummy memory cells and a second group of memory cells. Each of the first group of dummy memory cells having a first inverter assuming a first binary state is coupled to a first bit line, and has a first word line. The second group of dummy memory cells for acting as loading having a second inverter assuming a second binary state, each of the second inverter being coupled to the first bit line. Each of the second group of dummy memory cells having a second word line, the second word line of each of the second group of dummy memory cells is coupled to a source voltage level. The voltage on the two pairs of bit lines coupling to the array of dummy memory cells tracks the voltage drop on a normal bit line when the access signal arriving a normal memory cells coupled to the normal bit line.
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