发明名称 |
Method for forming a T-gate for better salicidation |
摘要 |
A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 mum and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting f (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process. A silicide layer is formed over the T-gate and the substrate to form silicide contacts to the SID regions and gate contacts to the T-gate. Then we form a dielectric layer (ILD) over the T-gate and substrate. We form contact opening through the dielectric layer to expose the S/D regions and T-gate. We form contacts to the S/D regions and to the T-gate.
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申请公布号 |
US6284613(B1) |
申请公布日期 |
2001.09.04 |
申请号 |
US19990434920 |
申请日期 |
1999.11.05 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
SUBRAHMANYAM CHIVUKULA;PRADEEP YELEHANKA RAMACHANDRAMURTHY;RAJAGOPAL RAMAKRISHNAN |
分类号 |
H01L21/336;H01L29/423;H01L29/78;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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