| 摘要 |
PURPOSE: A constant voltage generation circuit is provided to retain an output voltage of an initial current mirror as a level of an external voltage using a system reset signal(RST_SYS) and therefore to reduce a delay time spent in an initial driving of a sub-oscillator. CONSTITUTION: A current mirror part(10) induces a constant current and outputs it as the first constant voltage(VB). An inverter(INV) inverts a system reset signal(RST_SYS). A control PMOS transistor(CTPM) is turned on/off by the inverted system reset signal and retains an output(VB) of the current mirror part as an external voltage(VDD) level at an initial time. And an amplification part(20) amplifies the first constant voltage induced by the control PMOS transistor and outputs it as a constant voltage(VREG).
|
