发明名称 INSTRUCTION SEAQUENCE OPTIMIZING DEVICE AND ASSEMBLER DEVICE AND LINKER DEVICE AND INVERSE ASSEMBLER DEVICE AND DEBUGGER DEVICE AND COMPILER DEVICE AND RECORDING MEDIUM
摘要 PROBLEM TO BE SOLVED: To provide a processor for executing a program in which the units of the reading of an instruction and the execution of the instruction are made different from each other and a program developing environment for preparing the program. SOLUTION: When instruction decoders 409a-409c decode a branch instruction, the upper 29 bits of a PC relative value included in the branch instruction are transmitted to an upper priority PC arithmetic unit 411, and the lower 3 bits of the PC relative value are transmitted to a lower priority PC arithmetic unit 405. The lower priority PC arithmetic unit 405 adds or subtracts the present value of a lower priority PC 404 and the value of the lower 3 bits of the PC relative value, and transmits the arithmetic result as an updated value to the lower priority PC 404. The upper priority PC arithmetic unit 411 adds or subtracts the present value of an upper priority PC 403 and the value of the upper 29 bits of the PC relative value and carry from the lower priority PC arithmetic unit 405 as necessary, and transmits the arithmetic result as an updated value to the upper priority PC 403.
申请公布号 JP2001236235(A) 申请公布日期 2001.08.31
申请号 JP20010028234 申请日期 2001.02.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAKAYAMA SHUICHI;OGAWA HAJIME;KAWAGUCHI KENICHI;HIGAKI NOBUO;KOTANI KENSUKE;TANAKA TETSUYA;MIYAJI SHINYA;HEIJI TAKEHITO
分类号 G06F11/28;G06F9/45;(IPC1-7):G06F9/45 主分类号 G06F11/28
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