| 摘要 |
PROBLEM TO BE SOLVED: To establish both frequency performance and parallel performance by shortening memory wiring in a system for successively operating plural threads by arithmetic units arranged in a row in a processor using a multi- thread program, and to prevent inter-node data transfer interrupting the parallel processing performance and waiting through synchronization. SOLUTION: Plural caches for storing data are loaded on a processor carried by patent gazette 1999-287662, and each cache is connected to several arithmetic executing units. The contents of the cache are transferred and duplicated according to the progress of threads. When the contents of the cache can not completely transferred, one thread is executed by a single arithmetic executing unit. Moreover, access to the designated address is detected by using a virtual storage mechanism and the shared mechanism of the caches, and the threads are resumed.
|
