发明名称 SYNCHRONOUS INPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a synchronous input circuit capable of conforming to plural signal standards and a semiconductor integrated circuit capable of conforming to plural I/O interface standards. SOLUTION: This synchronous input circuit is constituted so as to supply an output signal of a selected master latch to a circuit at a rear stage by providing plural master latches 11A, 11B having different amplitude levels of signals to conform, a discrimination circuit 14 to discriminate a voltage level of impressed reference voltage Vref and a selecting means (clock synchronizing circuit 16) to select the master latch based on a discrimination result of the discrimination means. In addition, such a synchronous input circuit is integrated as an input circuit of an I/O cell of the semiconductor integrated circuit.</p>
申请公布号 JP2001236153(A) 申请公布日期 2001.08.31
申请号 JP20000047609 申请日期 2000.02.24
申请人 HITACHI LTD 发明人 MUTO TAKASHI;AIDA TATSUHIRO;TAKAHASHI TOSHIRO
分类号 G06F3/00;H03K3/3562;H03K19/0175;H03K19/096;(IPC1-7):G06F3/00;H03K19/017;H03K3/356 主分类号 G06F3/00
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