摘要 |
<p>PROBLEM TO BE SOLVED: To provide a synchronous input circuit capable of conforming to plural signal standards and a semiconductor integrated circuit capable of conforming to plural I/O interface standards. SOLUTION: This synchronous input circuit is constituted so as to supply an output signal of a selected master latch to a circuit at a rear stage by providing plural master latches 11A, 11B having different amplitude levels of signals to conform, a discrimination circuit 14 to discriminate a voltage level of impressed reference voltage Vref and a selecting means (clock synchronizing circuit 16) to select the master latch based on a discrimination result of the discrimination means. In addition, such a synchronous input circuit is integrated as an input circuit of an I/O cell of the semiconductor integrated circuit.</p> |