| 摘要 |
PROBLEM TO BE SOLVED: To suppress the breakdown voltage reduction of a gate insulation film due to steps at the boundary between an element isolation region and an active region. SOLUTION: The manufacturing method comprises forming trenches into a main surface of a semiconductor substrate 1, laminating a silicon oxide film for filling the trenches, applying the CMP method for polishing the silicon oxide film, while leaving the silicon oxide film only in the trenches to form a silicon oxide film 7 to be element isolation regions, removing the silicon oxide film utilized for forming the trenches, forming a victim oxide film, implanting ions, removing the victim oxide film, and dry etching to round the sectional shape of steps S at the boundary of the semiconductor substrate 1 (active region) and the silicon oxide film 7.
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