发明名称 CIRCUIT AND METHOD FOR EVALUATING PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a circuit and a method for evaluating a PLL circuit, with which the characteristics of a PLL circuit can be easily and accurately measured. SOLUTION: A low-pass filter 13 generates an oscillation control signal VCTRL on the basis of an output from a charge pump circuit 12. An analog/ digital converter 16 converts the supplied oscillation control signal VCTRL to a digital oscillation control signal VCTRL-D and supplies it to a lock detecting means 17. The lock detecting means 17 compares the supplied digital oscillation control signal with a digital oscillation control signal supplied the last time and when these values match continuously (m) times, a lock detecting signal MATCH ALL is turned to 'H' and outputted. As a result, the time from the input start of a reference signal CLK to the time when the lock detecting signal MATCH ALL is turned to 'H', can be detected as lock-up time T.
申请公布号 JP2001237696(A) 申请公布日期 2001.08.31
申请号 JP20000044965 申请日期 2000.02.22
申请人 NEC CORP 发明人 TAKESHITA YUICHI
分类号 H03L7/095 主分类号 H03L7/095
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