发明名称 RADIO COMMUNICATION SYSTEM
摘要 PROBLEM TO BE SOLVED: To solve the problem that frequency pull-in time fluctuates depending on switch timing of a frequency dividing ratio since it is not univocally defined whether the rise of an output (feedback side pulse) from a variable frequency divider is quickened or delayed rather than the rise of an output (reference side pulse) from a reference frequency divider after switching of the frequency dividing ratio in a conventional PLL circuit. SOLUTION: The radio communication system equipped with PLL circuits 132 and 133 having plural oscillation circuits 15A and 15B for processing at least two transmitting signals and receiving signals of different frequency bands by switching the oscillation circuits is provided with a reset means 17 for resetting the voltage of filter capacitor 14 to a prescribed voltage on the basis of a signal from a control means 150 when switching the oscillation circuits.
申请公布号 JP2001237699(A) 申请公布日期 2001.08.31
申请号 JP20000046200 申请日期 2000.02.23
申请人 HITACHI LTD 发明人 KASAHARA MASUMI;YAHAGI KOICHI
分类号 H03L7/089;H03L7/093;H03L7/14;H03L7/18;H04B1/00;H04B1/04;H04B1/40;H04L7/033 主分类号 H03L7/089
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