| 摘要 |
PROBLEM TO BE SOLVED: To provide a logical slowing/quickening device capable of executing normal logical slowing/quickening processing even when driving voltage is lowered. SOLUTION: This logical slowing/quickening device 100 is provided with a signal delay absorbing circuit 160 for absorbing a delay of a logical slowing/ quickening timing signal used for the formation of a start control signal, relative to a source oscillation signal. Since the signal delay absorbing circuit 160 eliminates the delay of the logical slowing/quickening timing signal FVCW relative to the source oscillation signal, even when the driving voltage of an IC is lowered, the start control signal VCW can be positively formed to realize normal logical slowing/quickening processing. Since the normal logical slowing/ quickening processing can be executed even when the driving voltage is lowered, the duration of a timepiece can be extended by that portion, and energy saving is also attained.
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