发明名称 |
METHOD AND ARCHITECTURE FOR OPTIMIZING DATA THROUGHPUT IN A MULTI-PROCESSOR ENVIRONMENT USING A RAM-BASED SHARED INDEX FIFO LINKED LIST |
摘要 |
A method and architecture for optimizing data throughput in a multiprocessor environment makes use of a RAM-based, shared index FIFO linked list, in which data to be processed is written to a central buffer and the index FIFO, constituting a linked list of indexes to the buffered data is passed between processing units within the system, providing a substantial reduction in the gate count required for processing the data. Messages are written to a central buffer; a linked list of indexes to the messages is created, and then pipelined to a processing unit as an index FIFO, so that the processor reads the entries of the linked list in sequence; as the entries are read, a message indicated by the entry is processed. Entries are enqueued and dequeued in an index FIFO RAM, so that enqueuing and dequeuing are performed in a single cycle with a single write operation.
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申请公布号 |
WO0104770(A3) |
申请公布日期 |
2001.08.30 |
申请号 |
WO2000US18939 |
申请日期 |
2000.07.11 |
申请人 |
ALTEON WEB SYSTEMS, INC.;LEE, KEITH;SCHMALTZ, DEAN |
发明人 |
LEE, KEITH;SCHMALTZ, DEAN |
分类号 |
G06F9/46;(IPC1-7):G06F9/46 |
主分类号 |
G06F9/46 |
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