发明名称 RECEIVER
摘要 A receiver comprising A/D converters (1-1 to 1-4) for converting received analog signals (I1, Q1, I2, Q2) into digital signals, a quantization error reducing signal generator (2) for generating quantization error reducing signals for random noises, adders (3-1 to 3-4) for adding converted digital signals to quantization error reducing signals, bit shift circuits (4-1 to 4-4) for reducing the number of bits of the added signals, low pass filters (5-1, 5-2) for removing quantization error reducing signals contained in the digital signals reduced in the number of bits, matched filters (6-1, 6-2), and a demodulator5 (7).
申请公布号 WO0163867(A1) 申请公布日期 2001.08.30
申请号 WO2001JP01262 申请日期 2001.02.21
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA;SUZUKI, TAKEO;ISHIOKA, KAZUAKI 发明人 SUZUKI, TAKEO;ISHIOKA, KAZUAKI
分类号 H03M1/12;H03D3/12;H03H17/02;H04B1/707;H04B7/26;H04J13/00;H04J13/18;H04L27/00;H04L27/38;H04W52/02;H04W88/02 主分类号 H03M1/12
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