发明名称 Semiconductor memory device allowing static-charge tolerance test between bit lines
摘要 A semiconductor memory device includes bit lines which transfer data of memory cells, a plurality of first sense amplifier circuits connected to odd-number lines of the bit lines, a plurality of second sense amplifier circuits connected to even-number lines of the bit lines, and a clamp-voltage generation circuit which supplies a first clamp voltage to the first sense amplifier circuits, and supplies a second clamp voltage to the second sense amplifier circuits, whereby during test operation, the odd-number lines are clamped to the first clamp voltage, and the even-number lines are clamped to the second clamp voltage.
申请公布号 US2001017807(A1) 申请公布日期 2001.08.30
申请号 US20010790573 申请日期 2001.02.23
申请人 FUJITSU LIMITED 发明人 FUJIOKA SHINYA
分类号 G11C11/401;G11C7/00;G11C29/00;G11C29/02;G11C29/06;H01L21/8242;H01L29/76;H01L29/94;H01L31/036;(IPC1-7):G11C7/00 主分类号 G11C11/401
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