发明名称 |
Semiconductor integrated circuit device with test interface circuit for performing test on embedded memory from outside |
摘要 |
A first test clock signal and a second test clock signal are generated from a common basic test clock signal using a delay line with a changeable delay time and a delay stage with a fixed delay time. A memory circuit is operated in synchronization with one of the first and second test clock signals, and the memory circuit is provided with a signal/data according to the other test clock signal. Thus, the set-up time and the hold time of a signal for the memory can be measured with accuracy in a memory-merged system LSI.
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申请公布号 |
US2001017814(A1) |
申请公布日期 |
2001.08.30 |
申请号 |
US20010782286 |
申请日期 |
2001.02.14 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ARIMOTO KAZUTAMI;SHIMANO HIROKI |
分类号 |
G01R31/28;G06F12/16;G11C11/401;G11C11/407;G11C29/02;G11C29/14;G11C29/48;G11C29/50;(IPC1-7):G11C8/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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