| 摘要 |
A co-processor for a DSP adapted for use with a DMT communication system. The co-processor includes a decoder for converting an input stream of QAM coordinated pairs into variable length sequences of bits and a combiner having a data register and an offset register for performing a cycle in which variable length bit sequences from the decoder are assembled into a block of data having a predetermined number of fixed length data words. An output buffer is provided for writing the data words into memory, whereby the data register can be preloaded with a part of a data word in memory, the offset register being set accordingly and the address register being set to the word-aligned address of the data word in memory, so that received data can be stored at a non-word aligned address.
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