| 摘要 |
Memory cell blocks respectively have a plurality of memory cell rows and a redundancy memory cell row for relieving a defect in these memory cell rows, memory cells being arranged in the memory cell rows. A first decoder selects any of the memory cell blocks. A second decoder selects any of the memory cell rows in the memory cell block. The operation of the second decoder not in use for decoding in the redundancy memory cell row is suspended when the redundancy memory cell row operates. The absence of unnecessary circuit operation allows a reduction in power consumption when the redundancy memory cell row operates. Even in a semiconductor integrated circuit having a plurality of memory banks each including the plurality of memory cell blocks, the first decoder, and the second decoder, it is possible to reduce power consumption when the redundancy memory cell rows operates.
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