发明名称 SEMICONDUCTOR STORAGE AND STRESS VOLTAGE SETTING METHOD
摘要 PURPOSE: To provide a semiconductor storage in which increasing circuit area can be prevented while being provided with a burn-in test function by which initial defect can be screened surely. CONSTITUTION: When either of a pair of dummy word lines DWL0, DWL1 arranged in a memory cell array is selected, minute potential difference is generated between bit lines BLZ and BLX by capacitive coupling between the dummy word lines DWL0, DWL1 and the bit lines BLZ, BLX. Stress voltage is supplied to the bit lines BLZ, BLX by amplifying minute potential difference by a sense amplifier 6.
申请公布号 KR20010082659(A) 申请公布日期 2001.08.30
申请号 KR20010007513 申请日期 2001.02.15
申请人 FUJITSU LIMITED 发明人 KATO YOSHIHARU;KAWAMOTO SATORU
分类号 G01R31/28;G11C11/401;G11C29/00;G11C29/06;G11C29/50;(IPC1-7):G11C29/00 主分类号 G01R31/28
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