发明名称 A Processor pipeline including instruction replay
摘要 The invention provides a method for executing instructions. The method includes dispatching and executing a first and second plurality of instructions in a portion of a pipeline without first determining whether stages of the portion of the pipeline are ready. The method further includes determining if an execution problem is encountered and replaying the first plurality of instructions in response to determining that the first plurality of instructions encountered an execution problem. The invention also provides a processor pipeline. The processor pipeline includes a front end to fetch a plurality of instructions for execution and a back end to execute the plurality of instructions fetched by the front end. The back end includes a retirement stage to determine if an instruction had an execution problem. The back end is non-stallable. The processor pipeline also includes a channel to send an indication that the instruction encountered an execution problem from the retirement stage to a replay point of the pipeline from which the instruction may be re-executed.
申请公布号 GB0116269(D0) 申请公布日期 2001.08.29
申请号 GB20010016269 申请日期 2000.01.05
申请人 INTEL CORPORATION 发明人
分类号 G06F9/38 主分类号 G06F9/38
代理机构 代理人
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