Synchronous switching circuit for data recovery

摘要

A switching circuit for switching an output (CKS) to one of a plurality of N input clock signals (CK1-CKN) which are delayed relative to one another comprises circuit means (31-316, 7) responding to a control (CNT) in order to enable the transmission, on the output signal (CKS), of a new signal (CK(i-1); CKi) of the plurality of input signals which is advanced or delayed relative to a current signal (CKi; CK(i-1)) of the plurality of input signals which is currently transmitted on the output signal (CKS), the circuit means (31-316, 7) enabling the transmission of the new signal (CK(i-1); CKi) before disabling the transmission of the current signal (CKi; CK(i-1)) on the output signal (CKS) so as to prevent the production of false signals during the switching of the output signal from one of the clock signals to another. <IMAGE>