发明名称 Semiconductor wafer with alignment mark sets and method of measuring alignment accuracy
摘要 <p>An alignment mark set (1-4) is provided, which facilitates the formation of a desired contour of each alignment mark and which suppresses the degradation of measurement accuracy for alignment of patterns. This alignment mark set comprises: (a) a first alignment mark (1) formed in an exposure area (7); the area having a periphery, first central axis (6), and a second central axis (5) perpendicular to the first axis; the first alignment mark being located near the first central axis and apart from the second axis; (b) a second alignment mark (2) formed in the exposure area; the second alignment mark being located near the second central axis and apart from the first axis; and (c) when the exposure areas are regularly arranged in such a way as to have a same orientation in a plane, each of the first and second alignment marks in one of the sets is not located close to the first and second alignment marks in another of the sets, thereby ensuring irradiation of exposing light to all the areas. It is preferred that each of the first and second marks is square. &lt;IMAGE&gt;</p>
申请公布号 EP1128215(A2) 申请公布日期 2001.08.29
申请号 EP20010103594 申请日期 2001.02.21
申请人 NEC ELECTRONICS CORPORATION 发明人 YOKOTA, KAZUKI
分类号 H01L21/027;G03F7/20;G03F9/00;(IPC1-7):G03F7/20 主分类号 H01L21/027
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