| 摘要 |
PURPOSE: A power-on reset circuit is provided to maintain a level of a power-on reset circuit and output a stable power-on reset signal by using a threshold voltage of a transistor. CONSTITUTION: A supply voltage(Vdd) is applied to a source of the first PMOS transistor(PM1). The supply voltage(Vdd) is applied to a source of the second PMOS(PM2). A gate of the PMOS transistor(PM1) is connected with a gate and a drain of the second PMOS transistor(PM2). Gates and drains of the third to the fifth PMOS transistors(PM3-PM5) are connected with the drain of the PMOS transistor(PM2). A drain of an NMOS transistor(NM) is connected with a drain of the first PMOS transistor(PM1). A source of the PMOS transistor(PM4) is connected with a gate of the NMOS transistor(NM). An inverter is connected with a common contact of the first PMOS transistor(PM1) and the NMOS transistor(NM).
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