| 摘要 |
A clock recovery circuit is provided for use in a memory with a clock synchronized interface or the like, wherein an external clock is temporarily intercepted to shorten the lock-in time when an internal clock is to be generated from the external clock.The clock recovery circuit includes a delay circuit array, into which an external clock is inputted, for generating a plurality of reference clocks, a control circuit for comparing the phases of the external clock and of the plurality of reference clocks and detecting the number of delay stages of the delay circuits required for locking in, and latching circuit for holding the number of delay stages required for locking in.Once synchronism is detected and the number of delay stages required for locking in are held in the latching circuit, the generation of the internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.
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