发明名称 Moire cancellation circuit
摘要 A circuit (300) for reducing Moiré effects in a display by delaying in alternate horizontal display lines a received horizontal drive pulse (HDRV IN), the circuit having: a current source arrangement (304, 314.1-314.n, 316.1-316.n) for tracking the display scanning speed and for producing a current which is representative of a binary input value (DVAL); a capacitor (308) arranged to be charged by the current; and a comparator (310) connected to the capacitor for delaying the received horizontal drive pulse by an amount dependent on the rate of charging of the capacitor. The circuit provides auto tracking with display scanning speed and programmability of the delay value. The circuit can be fabricated in integrated circuit form.
申请公布号 US6281889(B1) 申请公布日期 2001.08.28
申请号 US19980032990 申请日期 1998.03.02
申请人 MOTOROLA, INC. 发明人 CHEN JERRY
分类号 G09G1/04;H04N5/04;H04N5/21;H04N5/68;(IPC1-7):G09G5/00 主分类号 G09G1/04
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