发明名称 |
Delay locked loop circuit |
摘要 |
A delay locked loop circuit, comprising: first delay means for receiving an external clock signal to generate a delay clock signal; first oscillation means for generating a first pulse signal; second oscillation means for generating a second pulse signal; phase detection means for receiving the external clock signal and an internal clock signal and generating a phase detection signal; second delay means for delaying the delay clock signal by one period of the first pulse signal of the first oscillation means to generate a first plurality of clock signals; third delay means for delaying the delay clock signal by one period of the second pulse signal of the second oscillation means to generate a second plurality of clock signals; selection means for selecting a pair of clock signals having the same delay time from the first plurality of clock signals and the second plurality of clock signals; logic means for combining the pair of clock signals selected from the selection means to generate the internal clock signal; and control means for generating control signals for controlling the first delay means, the first and second oscillation means and the selection means and a reset signal for resetting the first and second delay means in accordance with the phase detection signal from the detection means.
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申请公布号 |
US6281728(B1) |
申请公布日期 |
2001.08.28 |
申请号 |
US20000545643 |
申请日期 |
2000.04.07 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES, CO., LTD |
发明人 |
SUNG JUN BAE |
分类号 |
G11C11/407;G11C7/22;H03K5/135;H03K5/15;H03L7/08;H03L7/081;(IPC1-7):H03L7/06 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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