Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods

摘要

Memory 200 having an array of rows and columns of memory cells, each column associated with a pair of complementary bitlines 302a, 302b. An access sense amplifier 203 coupled to each pair of complementary bitlines 302a, 302b for sensing and latching data from cells along a selected row during a first portion of a random access cycle. Refresh sense amplifier 204 is coupled to each pair of complementary bitlines for 302a, 302b for refreshing data from cells along a selected row during a second portion of the random access cycle.