发明名称 |
System decoder for high-speed data transmission and method for controlling track buffering |
摘要 |
A system decoder for high-speed data transmission in an optical disc reproducing apparatus. The system decoder includes a track buffer memory; a first FIFO (first-in, first-out) memory for receiving data descrambled and error-detected and outputting the data by a unit of plural words; a second FIFO memory for receiving data from the track buffer memory and outputting the data by the unit of plural words; and a track buffer controller writing the data in the first FIFO memory into the track buffer memory in a page mode, and reading the data written in the track buffer memory in a page mode to output the read data to the second FIFO memory. The track buffer memory includes a data area into which main data is written; an error information area into which error information for the main data is written; and a microcomputer area into which a microcomputer of the optical disc reproducing apparatus writes data.
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申请公布号 |
US6282367(B1) |
申请公布日期 |
2001.08.28 |
申请号 |
US19980007654 |
申请日期 |
1998.01.15 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHO CHAN-DONG;SHIM JAE-SEONG;JEONG JONG-SIK;KIM BYUNG-JUN |
分类号 |
G06F3/06;G11B20/10;G11B20/18;H04N5/85;H04N9/804;(IPC1-7):H04N5/781;H04N5/83 |
主分类号 |
G06F3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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